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Bit
3:2
Name
PARITY
Reset
0x0
Access
RW
Description
Parity-Bit Mode
Determines whether parity bits are enabled, and whether even or odd parity should be used.
Value
0
2
3
Mode
NONE
EVEN
ODD
Description
Parity bits are not used
Even parity are used. Parity bits are automatically generated and checked by hardware.
Odd parity is used. Parity bits are automatically generated and checked by hardware.
1
DATABITS
0
RW
Data-Bit Mode
This register sets the number of data bits.
Value
0
1
Mode
EIGHT
NINE
Description
Each frame contains 8 data bits
Each frame contains 9 data bits
0
AUTOTRI
0
RW
Automatic Transmitter Tristate
When set, LEUn_TX is tristated whenever the transmitter is inactive.
Value
0
1
Description
LEUn_TX is held high when the transmitter is inactive. INV inverts the inactive state.
LEUn_TX is tristated when the transmitter is inactive
18.5.2 LEUARTn_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Offset
0x004
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
CLEARRX
0
W1
Clear RX
Set to clear receive buffer and the RX shift register.
6
CLEARTX
0
W1
Clear TX
Set to clear transmit buffer and the TX shift register.
5
RXBLOCKDIS
0
W1
Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
4
RXBLOCKEN
0
W1
Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
3
TXDIS
0
W1
Transmitter Disable
Set to disable transmission.
2
TXEN
0
W1
Transmitter Enable
Set to enable data transmission.
1
RXDIS
0
W1
Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
2011-04-12 - d0001_Rev1.10
0
W1
233
Receiver Enable
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